5 research outputs found

    X-ray imaging in pin-in-paste technology

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    Today, pin-in-paste technology is used extensively. With the help of pin-in-paste, through-hole devices can be soldered using a standard surface mount technology (SMT) process and hereby a reduction in wave soldering is possible. This can result in cost savings and a decrease in production cycle time. To ensure successful pin-in-paste soldering the following steps must be taken: solder paste volume calculations for through-hole components; stencil aperture design for the pin-in-paste application; solder paste deposition through stencil printing, application of solder volume increasing techniques after printing; reflow profile optimization; inspections using special methods for each individual process; final tests. The paste is printed into the through-holes. For high quality pin-in-paste solder joints a sufficient volume of paste is a fundamental requirement. Nevertheless, after printing the through-hole-filling is usually unknown. In this paper a new method is described how to accurately determine the volume of solder alloy in solder paste that is present in the through-hole, using X-ray measurements, image processing and calculations. In addition, a method is suggested to determine the measuring characteristics and gray-scale linearity of the X-ray machine

    Feladatok 茅s megold谩sok a Hatvani Istv谩n fizikaversenyen

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    Solder Paste Scooping Detection by Multi-Level Visual Inspection of Printed Circuit Boards

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    In this paper we introduce an automated Bayesian visual inspection framework for Printed Circuit Board (PCB) assemblies, which is able to simultaneously deal with various shaped Circuit Elements (CE) on multiple scales. We propose a novel Hierarchical Multi Marked Point Process (HMMPP) model for this purpose, and demonstrate its efficiency on the task of solder paste scooping detection and scoop area estimation, which are important factors regarding the strength of the joints. A global optimization process attempts to find the optimal configuration of circuit entities, considering the observed image data, prior knowledge, and interactions between the neighboring CEs. The computational requirements are kept tractable by a data driven stochastic entity generation scheme. The proposed method is evaluated on real PCB data sets containing 125 images with more than 10.000 splice entities
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